Wireless networks are becoming increasingly power‑hungry, with a large portion of energy consumed by the transmitter. The ERC Synergy DISRUPT project aims to move RF‑power generation further into the digital domain and enable new transmitter concepts, provided that imperfections can be detected and corrected in real‑time.
In this PhD you will build the digital "brain" that makes this possible: an energy‑efficient, silicon‑proven AI/ML accelerator for transmitter error correction (digital predistortion/calibration). Your work will sit at the intersection of machine learning, DSP, and digital IC design, and you will validate your ideas on real chips alongside an international team. Excellent teamwork and smooth communication with colleagues are essential.
Responsibilities- Translate ML‑based error‑correction / DPD algorithms into hardware‑friendly forms (model reduction, sparsity, quantization, fixed‑point design).
- Design the architecture and RTL of a low‑power accelerator that meets tight throughput/latency constraints.
- Take the design through synthesis, layout, tape‑out, and support PCB bring‑up and measurements.
- Characterize the silicon in the lab: error‑correction performance, throughput, latency, and power.
- Contribute to joint demonstrators and publications with project partners.
You will be mentored day‑to‑day by Dr. Chang Gao (TU Delft) and co‑supervised by Prof. Anding Zhu (University College Dublin) and Prof. Leo de Vreede (TU Delft). This position directly connects to DISRUPT’s planned work on efficient ML‑based DPD, accelerator architecture, silicon tape‑out, and prototype measurements.
Requirements- MSc degree in Electrical / Electronic / Computer Engineering or a closely related field.
- Solid background in digital IC design and digital signal processing.
- Hands‑on RTL design skills (SystemVerilog / Verilog / VHDL) plus scripting (Python / MATLAB / C/C++).
- Strong command of English.
- Strong team player with excellent communication skills to collaborate smoothly with international colleagues.
- Practical experience with machine‑learning frameworks (e.g., PyTorch).
- Prior tape‑out experience (ASIC or a complex FPGA prototype) and familiarity with the digital back‑end flow (synthesis, P&R, timing closure).
- Knowledge of low‑power digital design techniques (e.g., clock/power gating, DVFS).
- A strong curiosity about RF transmitters, DPD algorithms, and analog/mixed‑signal challenges.
For more details about the DISRUPT project, visit https://elca.tudelft.nl/Research/project.php?id=243 and https://www.linkedin.com/posts/tu-delft-electrical-engineering-mathematics-and-computer-science_erc-ercsynergygrant-grant-activity-7392154613900013570-z60p/.
Your application will receive fair consideration.
Application procedureApply no later than 19 April 2026 via the application button and upload the following documents:
- CV
- Motivational letter (max. 1 page)
- BSc & MSc transcripts (courses and grades, English)
Contact: Dr. Chang Gao via chang.gao@tudelft.nl and Prof. Leo de Vreede via L.C.N.deVreede@tudelft.nl.
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