Junior FPGA Design Engineer

The Junior FPGA Design Engineer will contribute to the development of an advanced wireless communication system designed for long‑range, high‑data‑rate, and low‑latency performance. The role involves designing, integrating, and validating RTL modules while working closely with system architects and engineers across DSP, RF, and verification disciplines.

• Develop lint‑clean RTL modules based on system and algorithmic specifications.
• Integrate third‑party IP blocks and ensure proper functionality within the FPGA system.
• Review and refine RTL code quality to ensure complete functional coverage.
• Support the enhancement of internal FPGA design, verification, and testing methodologies.
• Debug timing issues and contribute to timing closure during STA.
• Perform on‑board debugging using logic analyzers and related tools.

• Relevant Master’s degree with 1–2 years of experience in FPGA or front‑end VLSI design.
• Proficiency in SystemVerilog.
• Working knowledge of C/C++ and Python.
• Experience with structured, lint‑clean RTL development.
• Understanding of wireless communication and signal processing concepts such as MIMO and OFDM.
• Familiarity with verification methodologies or tools such as CocoTB.
• Experience with fixed‑point DSP algorithm implementation in RTL is an advantage.

• Strong analytical and problem‑solving skills with attention to detail.
• Clear communication and ability to collaborate across technical domains.
• Eagerness to learn and adapt to evolving technologies.
• Commitment to high‑quality and innovative design practices.