In this exciting role, you are responsible for the delivery of fully verified layout designs (full custom), which meets all technical requirements provided by the designer. The main aspects in the standard analog based design flow are floor planning, transistor level layout and placement of IP, manual routing, full chip verification by DRC, LVS, ERC, package assembly rules and ESD/LU guidelines.
This is all done in a Cadence 5 design environment combined with appropriate tool and sub-micron process knowledge.
• Bachelor degree in Electronic Engineering
• 5+ year experience in Transistor Level IP and I/O Layout
• Skilled on with Cadence, Dracula and Assura Layout tooling
• Owns basic knowledge of Electro Static Discharge and Latch-Up mechanisms
• Experienced in submicron C100–like processes of the Semiconductor industry
• Good communication skills in both Dutch and English
• Target driven, shows initiative and can work independently.